New series demonstrates time-to-market innovation, embedding a full set of advanced features around a new core to deliver smartest STM32 MCUs ever
Headlining the industry’s most successful family of Cortex M-core-based microcontrollers, the new STM32 F7 MCU series operates at frequencies up to 200 MHz and uses a 6-stage superscalar pipeline and Floating Point Unit (FPU) to produce up to 1000 CoreMarks1. Architectural innovations surrounding the MCU boost performance and ease of use: ST has included two independent mechanisms to reach 0-wait-state performance from both internal and external memories: using ST’s Adaptive Real-Time (ART Accelerator™) for internal embedded Flash and L1 cache for both execution and data access from internal and external memories.
“ARM and ST have a long-standing and extensive business relationship, and it is exciting to see this extended to include MCUs based on the latest ARM Cortex-M7 processor,” said Noel Hurley, general manager, CPU group, ARM. “This partnership brings the benefits of the broadest ecosystem to a new set of performance- and reliability-demanding embedded applications.”
“ST has earned its place as the long-time leading supplier of Cortex-M MCUs by working closely with ARM as a lead partner and with our customers to ensure their time-to-market success,” said Daniel Colonna, STMicroelectronics Microcontroller Marketing Director. “The strength of our development ecosystem, the breadth of our MCU, sensor, power, and communications portfolios, and the technical support we deliver to customers makes the STM32 F7 the seamlessly accessible natural extension to top our industry-leading portfolio. The new level of internal- and external-memory performance gives developers new possibilities for innovation, as they no longer need to optimize their code for performance and memory.”
Manufactured on ST’s robust and production-proven 90nm embedded-non-volatile memory CMOS process technology2, the STM32 F7 series impressively demonstrates ST’s commitment to accelerate its own and customer innovation to meet time-to-market demands. At the same time, the advanced, future-proof architecture offers significant headroom to deliver far greater MCU performance as the Company moves to more advanced process geometries. The high-performance STM32F756NG MCU is sampling now to lead customers now and will be demonstrated at ST’s stand during ARM TechCon in Santa Clara, Oct 1-3, 2014.
Further Technical Information:
Surprisingly, the higher performance of the STM32 F7 has not impacted power efficiency. Despite greater functionality, the new series’ Run mode and low-power modes (STOP, Standby, and VBAT) consume current at the same low levels as the STM32 F4: 7 CoreMarks/mW in Run mode and, for low-power modes, down to 120 uA typical in STOP mode with all context and SRAM content saved, and 1.7uA typical in STANDBY mode and 0.1uA typical in VBAT mode.
In addition to ST’s ART Accelerator™ and 4Kbytes Instruction and Data caches, the STM32 F7 includes smart and flexible system architecture:
- An AXI and Multi-AHB (Advanced High-performance Bus) matrix with dual general-purpose DMA (Direct Memory Access) controllers and dedicated DMA controllers for Ethernet, USB OTG HS (Universal Serial Bus On-the-Go High Speed), and hardware acceleration of graphics via ST’s Chrom-ART Accelerator™;
- Available in 512kB and 1MByte embedded Flash to support applications that require large storage for code;
- Large SRAM with scattered architecture:
- 320 Kbytes including 240 Kbytes +16 Kbytes on the bus matrix for shared data and 64 Kbytes of Tightly-Coupled Memory (TCM) Data RAM for critical real-time data;
- 16-Kbytes of instruction TCM RAM for critical routines;
- 4 Kbytes of backup SRAM to keep data for the lowest power modes.
- STM32 F7 peripherals also include an independent clock domain to enable system-clock-speed changes without impacting communication speed;
- Flexible external memory controller with up to 32-bit data bus: SRAM,PSRAM,SDRAM/LPSDR, SDRAM, NOR/NAND memories;
- Dual Quad SPI interface for cost-effective memory extension even on lo- pin-count packages;
- Builds on the existing STM32 F4 series instruction set, delivering exclusively single-cycle Multiply and Accumulate (MAC) instructions and offering Single-Instruction Multiple Data (SIMD) instructions that work on 8- and 16-bit quantities packed into a 32-bit word.
For more information about the STM32 F7, visit www.st.com/stm32f7.
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1CoreMark is an industry-standard benchmark developed by the Embedded Benchmark Consortium (EEMBC) to measure MCU performance using a suite of application-code algorithms assembled to reflect real-world operation.
2The ST 90nm process has proven the most high-performing in the Cortex-M MCU space as demonstrated by superior CoreMark results ever since first STM32 F4 devices were launched in 2011.